Quality Assurance and Project Management

Aug 19 2019   9:55PM GMT

@Tachyum Joins PCI-SIG for Ultimate Performance of Data Center

Jaideep Khanduja Jaideep Khanduja Profile: Jaideep Khanduja


Tachyum joins PCI-SIG in order to optimize performance requirements of data center AI and HPC workloads. This highly scalable high-speed I/O solution by Tachyum is applicable to numerous market applications empowered by Tachyum’s processor Technology. Let us first understand what PCI and SIG stand for. PCI stands for peripheral component interconnect. SIG stands for a special interest group. As a matter of fact, this PCI-SIG comprises of over 700 member association that is committed for the advancement of the non-proprietary PCI Technology for high speed I/O in various market applications. As a matter of fact, the PCI expansion bus in today’s environment is by default and interconnect between CPUs and peripherals. With an increasing demand in higher performance I/O, scope and ecosystem reach of PCI expands tremendously. In fact, latest technology road maps including PCI Express focus on new form factors and lower-power applications.


There comes the role of association members who collaborate in open communities for the purpose of defining, testing, and refining specifications so that companies can bring to market PCI-compliant devices. As the innovation in PCIe Technology grows there is a continuous doubling of bandwidth availability to graphic cards, hard drives, Wi-Fi, Ethernet cards, SSDs, and so on. You must know that the fourth generation of the PCIe standard supports bandwidth capabilities of 64 GB per second. This if you notice is twice that of the PCIe 3.0 interface. Now let us understand that capabilities are of PCIe 5.0. it will double bandwidth rates to 128 GB per second. Tachyum is doing a great job in integrating PCIe based on customer requirements for storage, peer-to-peer clusters, AI, and as endpoints for accelerator applications.

Tachyum Joins PCI-SIG

With these advances to PCIe besides performance improvements, improved the support of the memory coherency created into the standard that protocols like CCIX and CXL get to multi-core processors. This ensures that all copies of data stay in a coherency. As a matter of fact, Tachyum’s Prodigy Universal Processor Chip empowers industry-leading advances in performance, energy consumption, space requirements, and data center server utilization. This happens in fully coherent multiprocessor environments utilizing PCIe. Amazingly Tachyum’s Prodigy Universal processor Chip is the smallest and fastest general-purpose 64-core processor produced till date. For that reason, it requires 10x less processor power and reduces processor cost by 3x. The Prodigy in fact directly enables 32 Tensor Exaflop supercomputer thereby allowing the creation of systems more powerful than the human brain by 2021. That will be one of the biggest landmarks in technology.

The data center TCO that is the annual total cost of ownership using prodigy reduces by 4x. All this happens because of Tachyum’s disruptive processor design embedded with a smart compiler that ultimately expels a number of parts of the hardware found in today’s typical processor as redundant. Ultimately it’s going to be fewer transistors, simpler core, fewer and shorter wires, greater speed, and huge power efficiency for the Prodigy processor. Basically, it is now businesses to decide when do they adopt Prodigy from Tachyum. Now to make things simpler or later when things complicate to a large extent.

Dr. Radoslav Danilak, CEO of Tachyum says, “Much has been made about the death of Moore’s Law and how the possibility to improve density, power efficiency and cost benefits in the semiconductor industry into the future is problematic. But the advances seen among PCI shows that this simply isn’t true. PCI-SIG already announced PCIe 6.0, which would double bandwidth again within 3 years. We, at Tachyum, will also ensure that the processor will not be the limiting factor either; it just requires a more innovative approach. We are glad to join the efforts of our fellow members in PCI-SIG in improving the speed capabilities of the next PCIe standard to support the performance needs of the data center, AI and Big Data workloads.”

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