IT Governance, Risk, and Compliance

Jul 21 2012   12:16AM GMT

IT Hardware Redundancy Checks Using Parity Bits – Part IV

Robert Davis Robert Davis Profile: Robert Davis

Reducing data reliability and integrity risks from IT hardware

When properly deployed, parity bits can be utilized to detect communication errors between IT hardware items. An advantage of the double parity bit is that an error is defined in two dimensions: vertical and horizontal. This permits the precise bit that is causing the error to be detected, thus enabling cybernetic error correction.

The redundancy check is a valuable control, however it is not foolproof. It is designed to detect mechanical, electronic and transmission sequence errors, but not to detect otherwise invalid data types. Furthermore, its reliability in error detection and correction is a function of the degree of built in redundancy. Therefore, the IT hardware user must determine the acceptable risk-level regarding receiving, storing, and transmitting accurate as well as complete datum, considering the IT architecture, then act accordingly.



Davis, Robert E. IT Auditing: Assuring Information Assets Protection. Mission Viejo, CA: Pleier Corporation, 2008. CD-ROM.

Gleim, Irvin N. CIA Examination Review. 3rd ed. Vol. 1. Gainesville, FL: Accounting Publications, 1989. 283-4

Watne, Donald A. and Peter B. B. Turney. Auditing EDP Systems. Englewood Cliffs, NJ: Prentice-Hall, 1984. 227-30

View Part I of the IT Hardware Redundancy Checks Using Parity Bits series here


Post Notes: “IT Hardware Redundancy Checks Using Parity Bits – Part IV” was originally published through under the title “IT Hardware Redundancy Checks Using Parity Bits”.


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