multicore processor

Details on the upcoming Power7 processor

IBM this week revealed details about its upcoming Power7 processor, confirming that it will be a 45-nanometer chip with 4, 6 or 8 cores. Each core will have up to 4 computing threads, meaning there could be up to 32 threads on a single Power7 chip.

The Power7 processor is expected out next year, with Steve Sibley, IBM Power Systems platform manager, saying IBM will try to get it out by mid-year. Other details on the chip: It will use DDR3 memory, have expanded cache and included embedded DRAM. Sibley wouldn’t disclose clock speeds but it is expected to be in the 3-4 GHz range. He said more details will come out at the HotChips conference next month in California.

Assuming the Power 595 server will retain its current architecture of up to 32 sockets, that means with Power7 chips it could have up to 256 processor cores and 1,024 computing threads.

Of course, IBM doesn’t want its Power Systems customers to wait around until the Power7 is released. So it announced a swap program. Users who have or buy a Power 570 or a Power 595 box now will be able to swap the Power7 processor book in for the Power6 or Power6+ processors they have there now. When I asked why lower-end systems weren’t involved in the swap program, Sibley said there is less interest among users in upgrading lower-end systems. When those servers get outdated, he said, end users tend to just move them to test and development environments.

Part of IBM’s goal is obviously to prevent the sales lull that often comes before a new chip release, but it also gives users options for buying now and swapping later without switching up the box’s serial number. In addition, swapping in the Power7 chips will not cost as much as buying a whole new box, though IBM hasn’t released any prices. Finally, the swap program is back-dated, so you don’t need to buy a box right now to get the swap. If you have a Power6 or Power6+ 570 or 595 now, you will be eligible for a serial-number protecting upgrade.

Intel set to release “Nehalem” Xeon processors

Intel may launch its next generation multi-core Xeon processors, code-named Nehalem, on Monday.

The company sent out invitations to a live webcast on March 30 “for the launch of a groundbreaking new server architecture.” If that doesn’t give it away, some server vendors have already announced products based on the Nehalem processors, including Cisco, which will use the Intel Xeon CPU’s in their upcoming Unified Computing System’s blade servers.  Rackable Systems already introduced CloudRack systems based on Nehalem, and Dell is expected to introduce Nehalem-based systems this week.

In earlier disclosures about Nehalem chips for x86 servers, Intel said the processor will have two, four or eight processing cores and provide better scalability than previous generations. It will also have scalable cache sizes and simultaneous multithreading, or Hyper-threading, which is already available on other Xeon processors.

While Intel prides itself on introducing multi-core processors at a faster pace than competitor AMD, some of the most significant enhancements to the new Xeon processor have existed in AMD chips for years.

For example, one of the major changes with Nehalem is integration of the memory controller into the CPU. This replaces the legacy Front Side Bus, which is a known culprit in traffic bottlenecks issues. AMD has been offering an integrated memory controller –called Direct Connect Architechture — in its Opteron CPUs for years now.

Another feature in Nehalem is the QuickPath Interconnect (QPI), which will give the chip faster access to a lot more bandwidth. This feature is similar to AMD’s HyperTransport technology, which has been around for a number of years as well.

That said, by adding QPI and an integrated memory controller, Nehalem will have access to a lot more bandwidth than its predecessors without relying on tons of cache memory, according to an ARS Technica report on Nehalem.

More importantly, what all of this means for end users is significantly better performance for applications that can take advantage of multithreading and multiple processing cores.