Data Center Apparatus

Sep 5 2013   7:26AM GMT

The trouble with server efficiency and performance

Erin Watkins Erin Watkins Profile: Erin Watkins

The tradeoff between the high cost of better performance and the forward-thinking energy efficiency is something IT shops must ponder when deciding what servers to buy. As chips shrink and become more efficient through manufacturing, the costs to chipmakers go up and those costs are passed on to buyers. So how can server chip design keep improving without incurring the cost of building whole new manufacturing facilities?

Researchers in China may help existing chip infrastructures become more efficient by improving the flow of electrons through semi-floating gates. All well and good, but both ARM and Intel boast fast, energy efficient server chips already and semi-floating gates are not a new concept.

transistors

Image by Flickr user Xeusy. Creative Commons license 2.0.

Let’s start with the Chinese team. In a paper published in Science Magazine, the researchers describe a way to use a hybrid of the floating gates found in flash memory and the traditional logic gates, which use complex rules to define which bits get through, and are used in most chips.

The researchers’ method is essentially a modification to the transistor’s isolation of the gate — floating gates are completely isolated from electron inputs and drains, where other gates are connected — and the research team says it can get better speed than current chips and has an energy efficient operating voltage of less than 2 Volts.

Looking at ARM and Intel chip efficiency improvements, it seems many of these come down to the fabrication process and less to the design of the chip itself. Take a recent ARM development by SuVolta, for example. It basically swapped out existing transistors for what it calls “Deeply Depleted Channel” transistors, which use dynamic body bias to reduce electric current leakage while the transistors are turned off. This isn’t necessarily a change to chip design, just switching out technology to consume less power.

Intel, on the other hand, is shifting manufacturing processes to 22 nanometer fabrication. This approach shrinks transistors and keeps them cooler during operation, thus helping to conserve energy. Instead of the side-by-side approach used by many chip makers, Intel has started stacking its transistors. This method improves performance and shortens the path of electricity on the chip, but producing 3D transistors requires up-front manufacturing investments, and may not provide enough return on investment to make it worth pursuing.

That’s the trouble with both SuVolta and Intel’s approaches. They rely on cost-prohibitive manufacturing processes to make smaller and more efficient chips. Every time a new transistor design is developed, a whole new set of equipment must be built. Plus, according to some analysts, Moore’s law is coming to an end, so smaller chips may not be a long term solution. Chip makers can only use manufacturing to boost efficiency for so long before they can’t shrink any further.

The current issues with return on investment for server chip manufacturing combined with the future limits of manufacturing technology are why the semi-floating gates proposed by the Chinese research team may be worth exploring — they’re not based on shrinking parts. For now, however, changes to chip fabrication seem to be making positive strides toward energy efficiency.

What do you think? Do prohibitive fabrication costs and a looming end to Moore’s law mean server chip makers need to find alternative methods for efficiency?

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